1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of Related Art
In recent years, along with a reduction in chip size, an area of an electrode pad used in probing and bonding has also been reduced. Besides, a ball area at a tip of a wire (gold wire) in the case of bonding the wire to the electrode pad has also been reduced, and thus a contact area between the ball and the electrode pad has been reduced as well. Therefore, when an electrode pad having a small area is used, if there remains damage caused by a probe on a surface of the electrode pad, there arises a problem in that bonding strength in the case of bonding the wire to the electrode pad is decreased.
In order to prevent a decrease in bonding strength described above, there is used an electrode pad including a probe area with which the probe is brought into contact at a time of testing, and a bonding area for bonding the wire after testing, which is different from the probe area. JP 11-074464 A describes two pads each including an assembly pad and a probe pad in combination and having sizes different from each other. In JP 11-074464 A, positions of probe pads of adjacent pads are displaced from each other, which enables, in the case of manufacturing a test probe card, probing with a small pitch even in a case where a diameter of a root portion of the probe is large.
Further, JP 02-241046 A describes a structure in which a pad for wire bonding and a pad for a wafer prober, which has a larger area compared with the pad for wire bonding, are individually provided. The pad for a wafer prober is subjected to probing, and then a wire connecting the pad for a wafer prober and the pad for wire bonding to an internal circuit is cut off.
The present inventor has recognized as follows. When the bonding region and the probing region are provided in different portions of the electrode pad, an area of the electrode pad needs to be nearly doubled compared with the case of performing probing and bonding in the same portion. An increase in area of the electrode pad leads to an increase in parasitic capacitance between the electrode pad and a semiconductor substrate. In an electrode pad to be connected to a circuit in which high frequency characteristics are valued, such an increase in parasitic capacitance poses a problem.